PIC18F14K50-I/SS【PDF 19/285 页】IC PIC MCU FLASH 8KX16 20-SSOP

收藏本站

您好，
买卖IC网欢迎您。
请登录
免费注册

买卖IC网

Sheet目录3876

15页 16页 17页 18页 [19页]20页 21页 22页 23页

2010 Microchip Technology Inc.

Preliminary

DS41350E-page 115

PIC18F/LF1XK50

FIGURE 13-2:

TIMER3 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)

13.2

Timer3 16-Bit Read/Write Mode

Timer3 can be configured for 16-bit reads and writes

(see Figure 13-2). When the RD16 control bit of the

T3CON register is set, the address for TMR3H is

mapped to a buffer register for the high byte of Timer3.

A read from TMR3L will load the contents of the high

byte of Timer3 into the Timer3 High Byte Buffer register.

This provides the user with the ability to accurately read

all 16 bits of Timer1 without having to determine

whether a read of the high byte, followed by a read of

the low byte, has become invalid due to a rollover

between reads.

A write to the high byte of Timer3 must also take place

through the TMR3H Buffer register. The Timer3 high

byte is updated with the contents of TMR3H when a

write occurs to TMR3L. This allows a user to write all

16 bits to both the high and low bytes of Timer3 at once.

The high byte of Timer3 is not directly readable or

writable in this mode. All reads and writes must take

place through the Timer3 High Byte Buffer register.

Writes to TMR3H do not clear the Timer3 prescaler.

The prescaler is only cleared on writes to TMR3L.

13.3

Using the Timer1 Oscillator as the

Timer3 Clock Source

The Timer1 internal oscillator may be used as the clock

source for Timer3. The Timer1 oscillator is enabled by

setting the T1OSCEN bit of the T1CON register. To use

it as the Timer3 clock source, the TMR3CS bit must

also be set. As previously noted, this also configures

Timer3 to increment on every rising edge of the

oscillator source.

The Timer1 oscillator is described in Section 11.0

“Timer1 Module”.

13.4

Timer3 Interrupt

The TMR3 register pair (TMR3H:TMR3L) increments

from 0000h to FFFFh and overflows to 0000h. The

Timer3 interrupt, if enabled, is generated on overflow

and is latched in interrupt flag bit, TMR3IF of the PIR2

setting or clearing the Timer3 Interrupt Enable bit,

TMR3IE of the PIE2 register.

T3SYNC

TMR3CS

T3CKPS<1:0>

Sleep Input

T1OSCEN(1)

FOSC/4

Internal

Clock

Prescaler

1, 2, 4, 8

Synchronize

Detect

T13CKI/T1OSI

T1OSO

Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.

TMR3L

Internal Data Bus

Set

TMR3IF

on Overflow

TMR3

TMR3H

High Byte

Read TMR1L

Write TMR1L

TMR3ON

CCP1 Special Event Trigger

Timer1 Oscillator

On/Off

Timer3

Timer1 Clock Input

CCP1 Select from T3CON<3>

Clear TMR3

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

采购需求

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

我的联系方式